As semiconductor devices scale to smaller dimensions, process complexity often increases to address device requirements. So-called replacement gate technology has been developed as an option for forming planar as well as fin type field effect transistors (finFET). The replacement gate approach forms a sacrificial gate using a sacrificial gate material, where the sacrificial gate is used to form device structures before being replaced by a final gate material. Known approaches using replacement gate process may also employ a self-aligned contact process, where the final gate metal is protected with an insulator cap during formation of contacts to the source/drain (S/D) region of the transistor.
A hallmark of the replacement gate process where the self-aligned contact process is also employed is the need to perform various polishing or planarization operations. A first planarization operation is used to polish and remove gate metal material from regions outside of the gate. A second planarization operation is used to polish and remove the insulator cap deposited on top of the gate metal, and used to electrically isolate the gate metal during S/D contact formation. These multiple planarization operations may be performed by chemical mechanical polishing (CMP), where a given CMP operation introduces gate height variation across different devices in a semiconductor chip, or across a semiconductor substrate (wafer). The combination of multiple CMP operations magnifies the gate height variation and accordingly reduces process margin in the self-aligned contact approach.
With respect to these and other considerations, the present disclosure is provided.